1 IDT74FCT3807/a 3.3v cmos 1-to-10 clock driver commercial/industrial temperature ranges september 2001 2001 integrated device technology, inc. dsc-4647/3 c IDT74FCT3807/a commercial/industrial temperature ranges 3.3v cmos 1-to-10 clock driver description: the fct3807/a 3.3v clock driver is built using advanced dual metal cmos technology. this low skew clock driver offers 1:10 fanout. the large fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. the fct3807/a offers low capacitance inputs with hysteresis for improved noise margins. multiple power and grounds reduce noise. typical applications are clock and signal distribution. functional block diagram in o 1 o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9 o 10 pin configuration gnd v cc gnd v cc gnd gnd v cc gnd o 5 v cc in o 1 o 2 o 3 o 4 o 10 o 9 o 8 o 7 o 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 soic/ ssop/ qsop top view features: ? 0.5 micron cmos technology ? guaranteed low skew < 350ps (max.) ? very low duty cycle distortion < 350ps (max.) ? high speed: propagation delay < 3ns (max.) ? very low cmos power levels ? ttl compatible inputs and outputs ? 1:10 fanout ? maximum output rise and fall time < 1.5ns (max.) ? low input capacitance: 4.5pf typical ?v cc = 3.3v 0.3v ? inputs can be driven from 3.3v or 5v components ? available in ssop, soic, and qsop packages the idt logo is a registered trademark of integrated device technology, inc.
2 commercial/industrial temperature ranges IDT74FCT3807/a 3.3v cmos 1-to-10 clock driver notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 3.3v, +25c ambient. 3. per ttl driven input (v in = v cc -0.6v); all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i c formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f i ) i cc = quiescent current (i ccl , i cch and i ccz ) ? i cc = power supply current for a ttl high input (v i n = v cc -0.6v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f i = input frequency all currents are in milliamps and all frequencies are in megahertz. absolute maximum ratings (1) symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to +7 v v term (4) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +60 ma notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. input terminals. 4. outputs and i/o terminals. capacitance (t a = +25 o c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf note: 1. this parameter is measured at characterization but not tested. pin description pin names description i n clock inputs o x clock outputs power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply current v cc = max. ? 10 30 a ttl inputs high v in = v cc ? 0.6v (3) i ccd dynamic power supply current (4) v cc = max. v in = v cc ? 0.31 0.45 ma/ input toggling v in = gnd mhz 50% duty cycle outputs open i c total power supply current (6) v cc = max. v in = v cc ? 15.5 22.8 ma input toggling v in = gnd 50% duty cycle outputs open v in = v cc ? 0.6v ? 15.5 22.8 fi = 50mhz v in = gnd
3 IDT74FCT3807/a 3.3v cmos 1-to-10 clock driver commercial/industrial temperature ranges dc electrical characteristics over operating range following conditions apply unless otherwise specified commercial: t a = 0c to +75c, industrial: t a = -40c to +85c, v cc = 3.3v 0.3v symbol parameter test conditions (1) min. typ. max. unit v ih input high level (input pins) guaranteed logic high level 2 ? 5.5 v input high level (i/o pins) 2 ? v cc + 0.5 v il input low level (input and i/o pins) guaranteed logic low level ?0.5 ? 0.8 v i ih input high current (input pins) v cc = max. v i = 5.5v ? ? 1 input high current (i/o pins) v i = v cc ?? 1a i il input low current (input pins) v cc = max. v i = gnd ? ? 1 input low current (i/o pins) v i = gnd ? ? 1 i ozh high impedence output current v cc = max. v o = v cc ?? 1a i ozl (3-state output pins) v o = gnd ? ? 1 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i odh output high current v cc = 3.3v, v in = v ih or v il , v o = 1.5v (3) ?36 ?60 ?110 ma i odl output low current v cc = 3.3v, v in = v ih or v il , v o = 1.5v (3) 50 90 200 m a v oh output high voltage v cc = min. i oh = ?0.1ma v cc ?0.2 ? ? v v in = v ih or v il i oh = ?8ma 2.4 (5) 3? v ol output low voltage v cc = min. i ol = 0.1ma ? ? 0.2 v in = v ih or v il i ol = 16ma ? 0.2 0.4 v i ol = 24ma ? 0.3 0.5 i off input power off leakage v cc = 0v, v in = 4.5v ? ? 1a i os short circuit current (4) v cc = max., v o = gnd (3) ?60 ?135 ?240 ma v h input hysteresis ? ? 150 ? mv i ccl quiescent power supply current v cc = max. ? 0.1 10 a i cch v in = gnd or v cc i ccz notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at vcc = 3.3v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is guaranteed but not tested. 5. v oh = vcc - 0.6v at rated current.
4 commercial/industrial temperature ranges IDT74FCT3807/a 3.3v cmos 1-to-10 clock driver notes: 1. see test circuits and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. t plh , t phl , t sk (t) are production tested. all other parameters guaranteed but not production tested. 4. propagation delay range indicated by min. and max. limit is due to v cc , operating temperature and process parameters. these propagation delay limits do not imply skew. fct3807 fct3807a symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay c l = 30pf 1.5 4.5 1.5 4 ns t phl f 67mhz t r output rise time (see figure 3) ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of ? 0.5 ? 0.35 ns same package (same transition) t sk(p) pulse skew: skew between opposite transitions ? 0.5 ? 0.35 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 1 ? 0.75 ns packages at same power supply voltage, temperature, package type and speed grade fct3807 fct3807a symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay c l = 50pf 1.5 4.8 1.5 4.3 ns t phl f 40mhz t r output rise time (see figure 4) ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of ? 0.5 ? 0.35 ns same package (same transition) t sk(p) pulse skew: skew between opposite transitions ? 0.5 ? 0.35 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 1 ? 0.75 ns packages at same power supply voltage, temperature, package type and speed grade switching characteristics over operating range - commercial (3,4) fct3807 fct3807a symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay 50 ? to v cc /2 1.5 3.5 1.5 3 ns t phl c l = 10pf t r output rise time (see figure 1) ? 1.5 ? 1.5 ns t f output fall time or 10 ? ac ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of te rmination, ? 0.5 ? 0.35 ns same package (same transition) c l = 50pf t sk(p) pulse skew: skew between opposite transitions (see figure 2) ? 0.5 ? 0.35 ns of same output (|t phl -? t plh |) f 100mhz t sk(t) package skew: skew between outputs of different outputs ? 0.9 ? 0.65 ns packages at same power supply voltage, connected in temperature, package type and speed grade groups of two
5 IDT74FCT3807/a 3.3v cmos 1-to-10 clock driver commercial/industrial temperature ranges notes: 1. see test circuits and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. t plh , t phl , t sk (t) are production tested. all other parameters guaranteed but not production tested. 4. propagation delay range indicated by min. and max. limit is due to v cc , operating temperature and process parameters. these propagation delay limits do not imply skew. fct3807 fct3807a symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay c l = 30pf 1.5 4.5 1.5 4 ns t phl f 67mhz t r output rise time (see figure 3) ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of ? 0.6 ? 0.45 ns same package (same transition) t sk(p) pulse skew: skew between opposite transitions ? 0.6 ? 0.45 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 1 ? 0.75 ns packages at same power supply voltage, temperature, package type and speed grade fct3807 fct3807a symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay c l = 50pf 1.5 4.8 1.5 4.3 ns t phl f 40mhz t r output rise time (see figure 4) ? 1.5 ? 1.5 ns t f output fall time ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of ? 0.6 ? 0.45 ns same package (same transition) t sk(p) pulse skew: skew between opposite transitions ? 0.6 ? 0.45 ns of same output (|t phl -? t plh |) t sk(t) package skew: skew between outputs of different ? 1 ? 0.75 ns packages at same power supply voltage, temperature, package type and speed grade switching characteristics over operating range - industrial (3,4) fct3807 fct3807a symbol parameter conditions (1) min . (2) max . min . (2) max . unit t plh propagation delay 50 ? to v cc /2 1.5 3.5 1.5 3 ns t phl c l = 10pf t r output rise time (see figure 1) ? 1.5 ? 1.5 ns t f output fall time or 50 ? ac ? 1.5 ? 1.5 ns t sk(o) output skew: skew between outputs of t ermination, ? 0.6 ? 0.45 ns same package (same transition) c l = 10pf t sk(p) pulse skew: skew between opposite transitions (see figure 2) ? 0.6 ? 0.45 ns of same output (|t phl -? t plh |) f 100mhz t sk(t) package skew: skew between outputs of different outputs ? 0.9 ? 0.65 ns packages at same power supply voltage, connected in temperature, package type and speed grade groups of two
6 commercial/industrial temperature ranges IDT74FCT3807/a 3.3v cmos 1-to-10 clock driver d.u.t. pulse generator v in v out v cc r t v cc 100 ? 100 ? 10pf d.u.t. pulse generator v in v out v cc r t 50 ? 10pf 220pf 30pf d.u.t. pulse generator v in v out v cc r t c l 50pf d.u.t. pulse generator v in v out v cc r t c l 50pf c l d.u.t. pulse generator v in v out v cc r t 500 ? 500 ? gnd 6v figure 1. z o = 50 ? ? ? ? ? to v cc /2, c l = 10pf the capacitor value for ac termination is determined by the operating frequency. for very low frequencies a higher capacitor value should be selected. figure 3. c l = 30pf circuit enable and disable time switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. figure 3. c l = 50pf circuit figure 2. z o = 50 ? ? ? ? ? ac termination, c l = 10pf test switch disable low 6v enable low disable high gnd enable high test circuits figure 5. enable and disable time circuit
7 IDT74FCT3807/a 3.3v cmos 1-to-10 clock driver commercial/industrial temperature ranges t plh1 output 1 output 2 t sk(o) t plh2 3v 0v v oh 1.5v 1.5v v ol v oh 1.5v v ol input t phl1 t phl2 t sk(o) t sk(o) = |t plh2 - t plh1 | or |t phl2 - t phl1 | control input output normally low output normally high 3v 1.5v 0v 3.5v 0v switch closed switch open v ol v oh 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable 3v 0v v oh t plh t phl v ol 1.5v 1.5v t r t f 2.0v 0.8v input output input t plh1 package 1 output package 2 output t sk(t) t plh2 3v 0v v oh 1.5v 1.5v v ol v oh 1.5v v ol t phl1 t phl2 t sk(t) t sk(t) = |t plh2 - t plh1 | or |t phl2 - t phl1 | t plh t phl 3v 0v v oh 1.5v 1.5v v ol t sk(p) = |t phl - t plh | input output test waveforms enable and disable times package 1 and package 2 are same device type and speed grade notes: 1. diagram shown for input control enable-low and input control disable-high 2. pulse generator for all pulses: f 1.0mhz; t f 2.5ns; t r 2.5ns pulse skew - t sk(p) package skew - t sk(t) package delay output skew - t sk(o)
8 commercial/industrial temperature ranges IDT74FCT3807/a 3.3v cmos 1-to-10 clock driver ordering information idt74fct temp. range xxxx device type x package 3.3v cmos 1-to-10 clock driver so sog py pyg q qg 3807 3807a small outline ic soic - green shrink small outline ic ssop - green quarter-size small outline ic qsop - green x blank i commercial (0c to +70c) industrial (-40c to +85c) corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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